The present invention relates to a solid state image sensing device comprising lateral type static induction transistors or vertical type static induction transistors.
Today, there have been widely used solid state image sensing devices comprising charge transfer elements such as BBD and CCD or MOS type transistors. However, the known solid state image sensing devices have various problems such as leakage of charge during the transfer, low photodetection sensitivity and low integration density. In order to avoid all the drawbacks of the known solid state image sensing devices, there has been proposed a solid state image sensing device comprising static induction transistors (hereinafter abbreviated as SIT). For instance, in a Japanese Patent Application Laid-open Publication No. 15,229/80, there is disclosed a solid state image sensing device comprising a number of SITs arranged in a matrix form, sources of the SITs being connected to row lines, drains being connected to column lines and gates being connected to a clear line. Further, in a solid state image sensing device comprising lateral static induction transistors (hereinafter abbreviated as LSIT), there has been developed an output system in which a light signal is directly derived as a common source configuration or a source follower configuration with a combination of a pixel and a resistor. For instance, in the Japanese Patent Application No. 59,525/84 filed on Mar. 29, 1984, there is proposed a solid state image sensor element. In this solid state image sensor-element, source and drain regions of a SIT are formed in a semiconductor layer applied on an insulating or highly resistive semiconductor substrate, and a gate region of the SIT is so formed in the semiconductor layer that it completely surrounds one of the source and drain regions, whereby a source-drain current flows in parallel with a surface of the semiconductor layer.
In the above Japanese Patent Application, there is further disclosed a solid state image sensing device comprising a number of image sensing elements each including an insulating or highly resistive semiconductor substrate, a semiconductor layer applied on the substrate source and drain regions formed in the semiconductor layer, and a gate region having at least a portion thereof formed between the source and drain regions, whereby a source-drain current flows in parallel with a surface of the semiconductor layer, and means for reverse biasing the source and drain regions during a time period for storing light signal.
Further, in the above Japanese Patent Application, there is proposed a solid state image sensing device comprising a number of solid state image sensor elements arranged in a matrix form, each element including a static induction transistor which comprises an insulating or highly resistive semiconductor substrate, a semiconductor layer formed on the substrate, source and drain regions formed in a surface of the semiconductor layer, a gate region having at least a part thereof formed between the source and drain regions, whereby a source-drain current flows in parallel with the surface of the semiconductor layer, and scanning means for biasing successive solid state image sensor elements in such a manner that during a light signal storing period used for storing photocarrier into the gate region, the source and drain region are reverse biased so as not to produce an output signal, and during a signal readout period the source or drain region is connected to ground to flow the source-drain current corresponding to the photocarriers stored in the gate region onto a video line.
Now the above mentioned solid state image sensing device will be further explained in detail. FIG. 1 is a circuit diagram showing a construction of a pixel of the solid state image sensing device compound of n-channel SITs connected as the common source configuration. In the drawing, a terminal 1 is a source terminal to which a source voltage V.sub.S is applied, and a terminal 2 is a drain terminal to which a drain voltage V.sub.D is applied. The terminal 2 is coupled with a drain electrode (D) via a load resistor R.sub.L and the drain electrode is further connected to an output terminal 5 from which an output voltage V.sub.OUT is derived. A terminal 3 constitutes a gate terminal and is connected to a gate electrode (G) upon which a light ray 7 is made incident. To a substrate terminal 8 is applied a substrate voltage V.sub.SUB.
FIGS. 2A to 2D are waveforms for explaining the operation of the solid state image sensor element shown in FIG. 1. FIG. 2A illustrates a change of the gate voltage V.sub.G applied to the gate terminal 3, FIG. 2B a change of the drain voltage V.sub.D applied to the drain terminal 2, FIG. 2C the source voltage V.sub.S applied to the source terminal 1, and FIG. 2D represents the substrate voltage V.sub.SUB applied to the substrate terminal 8. In the drawing a period of read out operation is denoted by T and is composed of store time T.sub.1, readout time T.sub.2 and reset time T.sub.3.
During the whole read out periods, the source voltage V.sub.S is maintained at ground voltage V.sub.S1 and the substrate voltage V.sub.SUB is kept at a reverse bias voltage V.sub.SUB1 (V.sub.SUB1 &lt;0). During the store time T.sub.1, the gate voltage V.sub.G remains at a deep reverse bias voltage V.sub.G1 (V.sub.g1 &lt;0) and thus, holes induced by the incident light ray 7 are stored in an interface between the semiconductor body and the insulating film immediately below the gate region. It should be noted that during the store time T.sub.1, the drain voltage V.sub.D is kept at ground voltage V.sub.D1. During the readout time T.sub.2 subsequent to the store time T.sub.1, the gate voltage V.sub.G is changed to a gate readout voltage V.sub.G2 (V.sub.G1 .ltoreq.V.sub.G2 &lt;0) and the drain voltage V.sub.D is changed into V.sub.D2 (V.sub.D2 &gt;0), so that the output signal is derived in accordance with an incident light amount. During the reset time T.sub.3 subsequent to the readout time T.sub.2, the gate voltage V.sub.G is changed to a forward biase voltage V.sub.G3 (V.sub.G3 &gt;0) and thus holes generated by the light input and stored below the gate are discharged. In the drawing, the drain voltage V.sub.D is maintained at the readout voltage V.sub.D2 during the reset time T.sub.3, but it may be the ground voltage V.sub.D1.
FIG. 3 is a graph showing the output voltage V.sub.OUT obtained at the outupt terminal 5 and the light amount l impinging upon the gate electrode 6. The light amount l is shown by a linear scale. When the light amount l is zero, the LSIT constituting the pixel is remained in the OFF condition and the output voltage V.sub.OUT is equal to the drain voltage V.sub.D. As the light amount l is gradually increased, the LSIT becomes more conductive and the output voltage V.sub.OUT is gradually decreased. When the light amount l becomes larger than a saturation value l.sub.1, the output voltage V.sub.OUT remains at a constant voltage V.sub.OUT1. Up to the saturation value l.sub.1, it has been experimentally confirmed that the output voltage V.sub.OUT .varies. the light amount l.
Now, the solid state image sensing device comprising a number of the above LSITs arranged in a matrix form will be explained with reference to FIGS. 4A to 4G. In the solid state image sensing device, the solid state image sensor elements arranged in a matrix form is raster-scanned to derive an image signal, there have been developed various scanning methods such as the drain-gate selection method, the source-gate selection method, and the source-drain selection method. Hereinbelow, the drain-gate selection method will be explained.
FIG. 4A is a circuit diagram showing a construction of the solid state image sensing device comprising the above mentioned LSITs arranged in a matrix form and FIGS. 4B to 4G illustrate signal waveforms for explaining the operation of the image sensing device. As shown in FIG. 4a, m.times.n LSITs 250-11, 250-12, . . ., 250-21, 250-22 . . ., 250-mn are arranged in a matrix form and are successively readout in accordance with the XY address system. Each pixel may be formed not only by a lateral static induction transistor having the gate region surrounding at least one of the source and drain regions, or by a lateral static induction transistor having the gate region formed between the source and drain regions. Source terminals of the LSITs are connected to ground, gate terminals of the LSITs arranged in the X direction are connected to respective row lines 251-1, 251-2 . . . 251-m, and drain terminals of the LSITs arranged in the Y direction are connected to respective column lines 252-1, 252-2 . . . 252-n. The column lines are commonly connected to a video line 254 and a ground line 254' via column selection transistors 253-1, 253-2, . . . 253-n and 253-1', 253-2' . . . 253-n', respectively. The video line 254 is further connected via a load resistor 255 to a video voltage source V.sub.DD. The row lines 251-1, 251-2 . . . 251-m are connected to a vertical scanning circuit 256 and are successively supplied with signals .phi..sub.G1, .phi..sub.G2 . . . .phi..sub.Gm. Gate terminals of the column selection transistors 253-1, 253-2 . . . 253-n and 253-1', 253-2' . . . 253-n' are connected directly and via inverters, respectively to a horizontal scanning circuit 257, and thus receive signals .phi..sub.D1, .phi..sub.D2 . . . .phi..sub.Dn and their inverted signals.
FIGS. 4B to 4D show the vertical scanning signals .phi..sub.G1, .phi..sub.G2 and .phi..sub.G3 and FIGS. 4E to 4G illustrate the horizontal scanning signals .phi..sub.D1, .phi..sub.D2 and .phi..sub.D3. Each of the vertical scanning signals .phi..sub.G1, .phi..sub.G2 . . . applied to the row lines 251-1, 251-2 . . . is comprised of a readout gate voltage V.sub..phi.G having a first amplitude and a reset gate voltage V.sub..phi.R having a second amplitude larger than the first amplitude. During a row scanning period t.sub.H, the scanning signal assumes the voltage V.sub..phi.G and during a horizontal blanking period t.sub.BL the scanning signal is set to the voltage V.sub..phi.R. The horizontal scanning signals .phi..sub.D1, .phi..sub.D2 . . . applied to the gate terminals of the column selection transistors are those for selecting the column lines 252-1, 252-2 . . . and assume a low level for cutting off the column selection transistors 253-1, 253-2 . . . and making conductive the anti-selection transistors 253-1', 253-2' . . ., and a high level for making conductive the column selection transistors and cutting off the anti-selection transistors.
When the vertical scanning signal .phi..sub.G1 supplied from the vertical scanning circuit 256 is changed to the voltage V.sub..phi.G, the LSITs 250-11, 250-12 . . . 250-1n connected to the row line 251-1 are selected. When the horizontal selection transistors 253-1, 253-2 . . . 253-n are made successively conductive by means of the signals .phi..sub.D1, .phi..sub.D2 . . . supplied from the horizontal scanning circuit 257, the output signals from the LSITs 250-11, 250-12 . . . 250-1n are successively read out on the video line 254. These LSITs 250-11, 250-12 . . . 250-1n are simultaneously reset when the signal .phi..sub.G1 is changed to the higher voltage V.sub..phi.R so as to prepare for a next light signal accumulating operation. Next when the signal .phi..sub.G2 becomes the voltage V.sub..phi.G, LSITs 250-21, 250-22 . . . 250-2n connected to the row line 251-2 are selected and are successively readout with the aid the horizontal scanning signals .phi..sub.D1, .phi..sub.D2 . . . .phi..sub.Dn, and after that are simultaneously reset when the signal .phi..sub.G2 is changed to the voltage V.sub..phi.R. In the manner explained above, successive LSITs are readout to obtain a video signal of one field.
In the solid state image sensing device, the higher the incident light is, the lower the output signal is obtained. That is to say, the output signal is derived as an inverted phase with respect to the input light signal. Therefore, the output signal always contains the output value V.sub.OUT-1 corresponding to the saturated input light. Therefore, the output signal has to be processed away from the solid state image sensor elements, and thus, it is necessary to provide additional external circuitry. Due to the fact that the video signals read out of the solid state image sensor elements have to be postprocessed by the external circuit, it becomes difficult to compensate variation between individual pixels and individual chips. Therefore, the manufacturing yield of the solid state image sensing device is low. Further, it is apparent that the manufacturing cost is increased due to the incorporation of the external circuit.